Serge Rabyking

Open silicon, built new in the open: imaging hardware from NumPy models, raw sensor transport over HDMI, and one engine for the file formats every EDA tool re-implements.

Speaking at ORConf 2026 — Ghent, September 11–13.

Building

np2hw NumPy image-processing models compiled to synthesisable, readable Verilog — held bit-exact against the model by an example suite that proves every capability. bayerlink Raw sensor data over any HDMI/DVI link: a self-describing protocol with conformance vectors, and tooling that closes the loop on a $10 capture stick. rawast One bidirectional, grammar-driven engine for the file formats every EDA tool re-implements: GDSII, LEF/DEF, Tcl, SystemVerilog. Grammars are data; the PoC parses 100% of a 3,132-file production corpus.

Setun-HDL The Setun-1958 — history's only production ternary computer — reimplemented in Amaranth from historical Soviet sources: CPU, ternary ALU, full toolchain, verified on a Tang Nano 9K. A book is in preparation; the source opens with it.

Background

Thirty-plus years of software coupled tightly to hardware — image processing, embedded systems, telephony, hardware products. Twelve years at Apical (acquired by Arm) working on image signal processing IP that shipped in production cameras — patent US10063787B2. At Apical I also built an image-pipeline compiler turning graphical models into C.

Doctoral research in logic optimisation (SAT) at Loughborough University; applied mathematics at MIPT. Founded and ran a hardware product company (2017–2023), designing and manufacturing its electronics and firmware. Merged upstream patches in open EDA tools.

Working with me

Consulting — ISP bring-up, imaging pipelines, EDA tooling — and sponsorship that funds named capability targets: the work lands open, with your name on the release.

Sponsor s.rabykin@gmail.com